al4ce2 11 / 221/ 23 1 /24 1/251 512, 1k, 2k, 4k , 8k x 9 advanced synchronous fifos applications - multimedia system - atm switches - routers - cable modems - wireless base stations - sonet(synchronous optical network) multiplexers - tbc(t ime base corrector) - hard disk cache memory description the al4ce2x1 series memory products are high - performance, low - power 9 bit read/write fifo (first - in - first - out) memory chip designed to buffer high speed streaming data for a wide range of applications. the al4ce2x 1 fifo memories are the advanced version of al4c s 2x 1 . retransmit is supported in t his product series to reduce designing efforts. ordering information part number al4ce2 11 , al4ce2 21 , al4ce2 31 , al4ce2 41 , al4ce2 51 package 32 - pin plastic tqfp power supply +3.3v 10% tqfp package top view averlogic al4ce2x1 x-xx-xx xxxx xxxx 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 features high performance, low - power, fifo(first - in first - out) memory 512 x 9 bit i/o port (al4ce21 1 ) 1k x 9 bit 1/o port (al4ce22 1 ) 2k x 9 bit i/o port (al4ce23 1 ) 4k x 9 bit i/o port (al4ce24 1 ) 8k x 9 bit i/o port (al4ce251) high clock speed ( 133mhz) fully independent read/write access retransmit the data (reread the data) empty, full, and programmable almost empty, almost full flags output enable control (data skipping) 3.3v power with 5v signal tolerant input standard 32 - pin tqfp
a ver l ogic t echnologies , i nc . tel : 1 40 8 361 - 0400 e - mail: sales@averlogic.com url: www.averlogic.com march 26, 2002 (512, 1k ,2k, 4k, 8k) x9 memory array input buffer output buffer write control logic read control logic flag logic control logic write pointer read pointer offset regissers reset logic input data bus output data bus /oe wclk /wen /ld /rs rclk /ren /ff /ef /paf /pae /rt figure 1. al4ce2x1 fifo block diagram the 9 bit input and output ports operate independently at a maximum speed of 133 mhz. the built - in address decoder and pointer managing circuits provide a straightforward bus interface to serially read/write memory that reduces inter - chip design efforts. the al4ce2x 1 embedded memory array and high performance process technologies with extended controller functions (read skip, fixed and programmable status flags.. etc.) offer flexible me mory management. these fifos support 9 bit input and output data bus - width that is controlled by separate clock and enable signals respectively. the input data is acquired at each rising edge of a free running write clock while a write enable control pi n is asserted. the output data is available after each rising edge of a free running read clock while a read enable and output enable control pins are asserted. when output enable (/oe) is low, the data output bus is active. if /oe is high, the output d ata bus will be in a high - impedance. this signal can control whether the data is going to be skipped during the read operation. the fifo full/empty and programmable almost full/almost empty flags are functions that can help controlling software to manip ulate the fifo more easily or to do retransmit operation. and the retransmit function allows data to be reread from the fifo more than once. these chips are available as a 32 pin tqfp package d istributed by :
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